An energy-efficient instruction scheduler design with two-level shelving and adaptive banking yu-lai zhao, xian-feng li, dong tong, and xu cheng 采用两级缓置和自适应多体技术的能耗有效的指令调度器设计
Mainstream processors implement the instruction scheduler using a monolithic cam-based issue queue, which consumes increasingly high energy as its size scales . in particular, its instruction wakeup logic accounts for a major portion of the consumed energy 调度逻辑主要由唤醒和选择两部分构成,而基于cam队列的唤醒逻辑能耗是主要的,唤醒逻辑的能耗主要来源是发射队列中的标签比较器。